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| PSMN005-30K TrenchMOSTM logic level FET Rev. 01 -- 6 March 2002 Product data 1. Description SiliconMAXTM products use the latest Philips TrenchMOSTM technology to achieve the lowest possible on-state resistance in a SOT96-1 (SO8) package. Product availability: PSMN005-30K in SOT96-1 (SO8). 2. Features s Very low on-state resistance s Fast switching s TrenchMOSTM technology. 3. Applications s DC to DC convertors s Computer motherboards s Switch mode power supplies. 4. Pinning information Table 1: Pin 1,2,3 4 5,6,7,8 Pinning - SOT96-1, simplified outline and symbol Description source (s) gate (g) drain (d) g 1 Top view 4 MBK187 Simplified outline 8 5 Symbol d MBB076 s SOT96-1 (SO8) Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions Tj = 25 to 150 C Tsp = 80 C Tsp = 80 C VGS = 10 V; ID = 15 A; Tj = 25 C Typ 4.4 Max 30 20 3.5 150 5.5 Unit V A W C m drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature operating junction temperature source (diode forward) current (DC) Tsp = 80 C peak source (diode forward) current Tsp = 25 C; pulsed; tp 10 s Tsp = 80 C; VGS = 10V Tsp = 25 C; pulsed; tp 10 s Tsp = 80 C Conditions Tj = 25 to 150 C Min -55 -55 Max 30 20 20 60 3.5 +150 +150 20 60 Unit V V A A W C C A A Source-drain diode 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 2 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 120 Pder (%) 80 03aa17 03aa25 120 Ider (%) 80 40 40 0 0 50 100 150 Tsp (C) 200 0 0 50 100 150 Tsp ( C) o 200 P tot P der = ---------------------- x 100% P tot ( 25 C ) ID I der = ------------------- x 100% I D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 103 ID (A) 102 RDSon = VDS / ID tp = 10 s 100 s 10 1 ms 10 ms 1 100 ms 03ah05 DC 10-1 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 3 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 7. Thermal characteristics Table 4: Rth(j-sp) Thermal characteristics Conditions Min Typ Max Unit 20 K/W thermal resistance from junction to solder point mounted on a metal clad board; Figure 4 Symbol Parameter 7.1 Transient thermal impedance 102 03ah04 Zth(j-sp) (K/W) 10 = 0.5 0.2 0.1 1 0.05 0.02 tp T t P = tp T single pulse 10-1 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 4 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 C unless otherwise specified Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage ID = 250 A; VGS = 0 V ID = 1 mA; VDS = VGS Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain-source leakage current VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 10 V; ID = 15 A Tj = 25 C VGS = 4.5 V; ID = 13 A Tj = 25 C Dynamic characteristics gfs Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr forward transconductance total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 15 A; VGS = 0 V reverse recovery time recovery charge IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V VDD = 15 V; RL = 15 ; VGS = 10 V; RG = 6 VGS = 0 V; VDS = 25 V; f = 1 MHz VDS = 15 V; ID = 20 A ID = 20 A; VDD = 15 V; VGS = 4.5 V 60 34 15 14 605 405 18 16 65 45 0.81 35 20 1.3 S nC nC nC pF pF pF ns ns ns ns V ns nC 6.6 8 m 4.4 5.5 m 1 0.5 100 A mA nA 1 0.5 3 3.4 V V V 30 V Conditions Min Typ Max Unit 3100 - Source-drain (reverse) diode 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 5 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 03ah06 03ah08 60 10 V 4.5 V ID (A) 3.8 V 40 4V 60 ID (A) 40 VDS > ID x R DSon 3.6 V 20 3.4 V 3.2 V 20 Tj = 150 C VGS = 3 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 25 C 0 0 1 2 3 4 VGS (V) 5 Tj = 25 C Tj = 25 C and 175 C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03ah07 0.02 RDSon () 0.016 Tj = 25 C VGS = 3.8 V 4V 2 a 1.6 03af18 0.012 1.2 0.008 4.5 V 0.004 10 V 0.8 0.4 0 0 20 40 ID (A) 60 0 -60 0 60 120 Tj (C) 180 Tj = 25 C R DSon a = ---------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function of drain current; typical values. 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 6 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 03af65 4 10-1 03af66 max 3 10-2 10-3 typ 2 10-4 min 1 10-5 min typ max 0 -60 0 60 120 180 10-6 0 1 2 3 4 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 104 03ah10 C (pF) Ciss 103 Coss Crss 102 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 7 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 03ah09 03ah11 60 IS (A) 40 VGS = 0 V 10 VGS (V) 8 ID = 20 A Tj = 25 C VDD = 15 V 6 4 20 2 150 C 0 0 0.4 0.8 VSD (V) 1.2 Tj = 25 C 0 0 20 40 60 QG (nC) 80 Tj = 25 C and 175 C; VGS = 0 V ID = 20 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 8 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 9. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index Lp 1 e bp 4 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 0.028 0.004 0.012 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 Fig 14. SOT96-1 (SO8). 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 9 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 10. Revision history Table 6: Rev Date 01 20020306 Revision history CPCN Description Product Data; initial version 9397 750 09334 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 10 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET 11. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 13. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 14. Trademarks SiliconMAX -- is a trademark of Koninklijke Philips Electronics N.V. TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 09334 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 6 March 2002 11 of 12 Philips Semiconductors PSMN005-30K TrenchMOSTM logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 6 March 2002 Document order number: 9397 750 09334 |
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